Semiconductor input protection circuit

ABSTRACT

A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D 1  is formed. In the transistor NB, a diode D 3  is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D 3 , whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D 1 .

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based on and claims priority on Japanesepatent application 2000-317557, filed on Oct. 18, 2000, the wholecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to an input protection circuit forprotecting an input circuit portion of an integrated circuit device suchas CMOSIC from breakdown by electro-static discharge (ESD) or the like.

[0004] 2. Description of the Related Art

[0005] A conventional input protection circuit used for CMOSIC or thelike has a MOS transistor whose drain is connected to an input terminalof CMOSIC or the like and whose gate and source are connected to theground potential. The gate insulating film of the MOS transistor of suchan input protection circuit has a low breakdown voltage of about 10 V sothat an ESD breakdown voltage is low.

[0006] An input protection circuit having a higher ESD breakdown voltagehas been proposed such as shown in FIGS. 10 and 11. In FIGS. 10 and 11,reference characters IN represent an input terminal from which an inputsignal is supplied to a circuit to be protected.

[0007] In the circuit shown in FIG. 10, in one principal surface area ofa p-type silicon substrate 1, a p-type well region 2 is formed in whichn-type well regions 3 and 4 are formed. A MOS transistor is formed bythe n-type well regions 3 and 4 and a channel made of a portion of thep-type well region 2. The bottoms of both the n-type well regions 3 and4 form PN junctions with the substrate 1. In the well regions 3 and 4,n⁺-type impurity doped regions 5 and 6 are formed to provide contactregions, and in the p-type well region 2, a p⁺-type impurity dopedregion 7 is formed to provide a contact region.

[0008] On the principal surface of the substrate 1, a field insulatingfilm 8 made of silicon oxide or the like is formed. On the insulatingfilm 8 above the channel region between the well regions 3 and 4, a gateelectrode layer 9 made of polysilicon or the like is formed. Theimpurity doped region 5 and gate electrode layer 9 are connected to theinput terminal IN. The impurity doped regions 6 and 7 are both connectedto the ground potential.

[0009]FIG. 11 is an equivalent circuit diagram of the integrated circuitstructure shown in FIG. 10. The drain and gate (well region 3 and gateelectrode layer 9 shown in FIG. 10) of an n-channel MOS type transistorFT are connected to the input terminal IN. The source (well region 4shown in FIG. 10) of the transistor FT is connected to the groundpotential. A diode D is formed between the well region 3 and substrate1, the cathode and anode thereof being connected to the input terminalIN and ground potential, respectively. An NPN type lateral bipolartransistor BT is made of the well regions 3 and 4 and a p-type region (aportion of the well region 2) between the well regions 3 and 4, thecollector and emitter thereof being connected to the input terminal INand ground potential, respectively. Between the base and emitter of thetransistor BT, a resistor R made of the resistance components of thesubstrate is connected. The well region 2 and substrate 1 are connectedto the ground potential.

[0010] When an ESD input of +V is applied to the input terminal IN, thetransistor FT turns on to protect a subject circuit CP to be protected.Since the thick field insulating film 8 is used as the gate insulatingfilm of the transistor FT, it has a high ESD breakdown voltage. In thisspecification, the term “ESD input” is intended to mean “a surge voltageinput caused by static electricity or the like”.

[0011] The diode D is made of a PN junction between well regions 3 and 2and between the well region 3 and substrate 1 (i.e., PN junctions formedbetween low impurity concentration regions) so that it has a highinverse breakdown voltage of about 50 V. The level of a positive signalcapable of being input to the subject circuit to be protected is limitedby the inverse breakdown voltage of the diode D. When an ESD input of −Vis applied to the input terminal IN, the diode D turns on to protect thesubject circuit CP to be protected.

[0012] In the field of audio circuits, CMOSIC is generally required toprocess a signal in the range from +15 V to −15 V. With the conventionalcircuit described above, although a +15 V input signal can be processed,a −15 V input signal cannot be input because a negative input signalturns on the diode D.

SUMMARY OF THE INVENTION

[0013] It is an object of the present invention to provide a novel inputprotection circuit having a high ESD breakdown voltage and being capableof inputting positive and negative input signals in a broad input signallevel range.

[0014] According to one aspect of the present invention, there isprovided an input protection circuit comprising: an input terminal forsupplying an input signal to a circuit to be protected; a semiconductorsubstrate of a first conductivity type; a first well region of a secondconductivity type opposite to the first conductivity type, the firstwell region being formed in one principal surface area of thesemiconductor substrate and forming a PN junction with the semiconductorsubstrate; first and second impurity doped regions of the firstconductivity type formed in the first well region and forming a firstlateral bipolar transistor with a portion of the first well regionserving as a base; a second well region of the first conductivity typeformed in the principal surface area of the semiconductor substrate; andthird and fourth well regions of the second conductivity type formed inthe second well region and forming a second lateral bipolar transistorwith a portion of the second well region serving as a base, bottoms ofthe third and fourth well regions forming a PN junction with the secondwell or with the semiconductor substrate, wherein the input terminal isconnected to the first impurity doped region, the second impurity dopedregion and the base of the first lateral bipolar transistor areconnected to the third well region, and the fourth well region and thebase of the second lateral bipolar transistor are connected to areference potential.

[0015] If the first and second conductivity types of the inputprotection circuit are p- and n-types, respectively, when an ESD inputof +V is applied, the second lateral bipolar transistor turns on,whereas when an ESD input of −V is applied, the first lateral bipolartransistor turns on. The circuit can be protected from an ESD input of,e.g., ±2000 V. The level of a positive signal capable of being input islimited by the inverse breakdown voltage of a PN junction diode formedbetween the second and third well regions (or between the second wellregion and semiconductor substrate). Since the PN junction is formed inthe well regions having a low impurity concentration, the inversebreakdown voltage of the diode can be set to, for example, about 50 V.The level of a negative signal capable of being input is limited by theinverse breakdown voltage of a PN junction diode formed between thefirst impurity doped region and first well region. The inverse breakdownvoltage of the diode can be set to, for example, about 15 V. It istherefore possible to input a signal in the range from +15 V to −15 V.

[0016] In the input protection circuit, a current limiting resistor maybe formed on an insulating layer formed on the principal surface of thesemiconductor substrate to connect the input terminal to the firstimpurity doped region via the current limiting resistor. Thermalbreakage of transistors and diodes constituting the input protectioncircuit can be avoided.

[0017] In the input protection circuit, the first and second lateraltransistors may be exchanged.

[0018] According to another aspect of the present invention, there isprovided an input protection circuit comprising: an input terminal forsupplying an input signal to a circuit to be protected; a semiconductorsubstrate of a first conductivity type; a first well region of a secondconductivity type opposite to the first conductivity type, the firstwell region being formed in one principal surface area of thesemiconductor substrate and forming a PN junction with the semiconductorsubstrate; first and second impurity doped regions of the firstconductivity type formed in the first well region and forming a firstlateral bipolar transistor with a portion of the first well regionserving as a base; and second and third well regions of the secondconductivity type formed in the principal surface area of thesemiconductor substrate, the second and third well regions forming asecond lateral bipolar transistor with a portion of the semiconductorsubstrate serving as a base, wherein the input terminal is connected tothe first impurity doped region, the second impurity doped region andthe base of the first lateral bipolar transistor are connected to thesecond well region, and the third well region and the base of the secondlateral bipolar transistor are connected to a reference potential.

[0019] In this input protection circuit, the second well region of theinput protection circuit described earlier is omitted. This inputprotection circuit can have similar operations and advantages to thoseof the input protection circuit described earlier. One of two PNjunction diodes which determine the range of a signal level capable ofbeing input, is formed between the second well region and semiconductorsubstrate. Therefore, the inverse breakdown voltage of this diode can beraised and the range of a signal level capable of being input can bebroadened further.

[0020] In the input protection circuit, a current limiting resistor maybe formed on an insulating layer formed on the principal surface of thesemiconductor substrate to connect the input terminal to the firstimpurity doped region via the current limiting resistor. Thermalbreakage of transistors and diodes constituting the input protectioncircuit can be avoided.

[0021] Similar to the input protection circuit described earlier, thefirst and second lateral transistors may be exchanged.

[0022] As above, an input protection circuit having a high ESD breakdownvoltage of ±2000 V and being capable of inputting a signal in a broadinput signal level range of ±15 V can be provided. An integrated circuitdevice used in the field of audio circuits or the like can be protectedreliably.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a cross sectional view of a substrate showing anintegrated structure of an input protection circuit according to anembodiment of the invention.

[0024]FIG. 2 is an equivalent circuit diagram of the integratedstructure shown in FIG. 1.

[0025]FIG. 3 is a top view showing an example of theemitter-base-collector layout of an NPN type transistor.

[0026]FIG. 4 is a top view showing another example of theemitter-base-collector layout of an NPN type transistor.

[0027]FIG. 5 is an equivalent circuit diagram of an NPN type transistorhaving the layout shown in FIG. 4.

[0028]FIG. 6 is a graph showing an example of the voltage-currentcharacteristics of the circuit shown in FIG. 1.

[0029]FIG. 7 is an equivalent circuit diagram showing a firstmodification of the integrated structure shown in FIG. 1.

[0030]FIG. 8 is a cross sectional view of a substrate showing a secondmodification of the integrated structure shown in FIG. 1.

[0031]FIG. 9 is an equivalent circuit diagram of the integratedstructure shown in FIG. 8.

[0032]FIG. 10 is a cross sectional view showing the integrated structureof a conventional input protection circuit.

[0033]FIG. 11 is an equivalent circuit diagram of the integratedstructure shown in FIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034]FIG. 1 shows the integrated structure of an input protectioncircuit according to an embodiment of the invention.

[0035] A p-type semiconductor substrate 10 made of, e.g., silicon, has arelatively low impurity concentration (e.g., 10¹⁵cm⁻³ or lower) and hasan n-type well region 12 formed in its one principal surface area. Thewell region 12 has a relatively low impurity concentration (e.g., 4×10¹⁶to 1×10¹⁷cm⁻³) and is formed by selective ion implantation or the like,forming a PN junction with the substrate 10.

[0036] In the well region 12, p⁺-type impurity doped regions 14 and 16are formed to form a PNP type lateral bipolar transistor PB with aportion of the well region 12 serving as its base. The impurity dopedregions 14 and 16 have a relatively high impurity concentration (e.g., 1to 5×10²¹cm⁻³) and is formed by selective diffusion, selective ionimplantation or the like.

[0037] In the well region 12, an n⁺-type impurity doped region 18 forproviding an ohmic contact is formed. The impurity doped region 18 has arelatively high impurity concentration and is formed by selectivediffusion, selective ion implantation or the like.

[0038] In the principal surface area of the substrate 10, a p-type wellregion 20 is formed having a relatively low impurity concentration(e.g., 4×10¹⁶ to 1×10¹⁷cm⁻³). Although this well region 20 is shown tohave a PN junction at its side with the well region 12, it may be formedspaced apart from the well region 12, as shown by a broken line.

[0039] In the well region 20, n-type well regions 22 and 24 are formedto form an NPN type lateral bipolar transistor NB with a portion of thewell region 20 serving as its base. The well regions 22 and 24 have arelatively low net impurity concentration (e.g., 4×10¹⁶ to 1×10¹⁷cm⁻³)and is formed by selective ion implantation or the like, whichover-compensates the impurity concentration of the well 20, forming a PNjunction with the substrate 10. The well regions 22 and 24 can be formedby the same process as the process of forming the well region 12.Although both the well regions 22 and 24 form PN junctions with the wellregion 20 and substrate 10, they may be formed to have the PN junctionsonly with the well region 20 (to have the PN junction not with thesubstrate 10 but only with the well region 20 at the bottoms of the wellregions 22 and 24, as shown by broken lines).

[0040] In the well regions 22 and 24, n⁺-type impurity doped regions 26and 28 are formed to provide ohmic contacts. Both the impurity dopedregions 26 and 28 have a relatively high impurity concentration and canbe formed by utilizing the same process as that of forming the impuritydoped region 18. If impurity doped regions are formed by the sameprocess in regions having different conductivity types and impurityconcentrations, the impurity concentrations and impurity doped depths ofthe regions formed by the same process are different more or less.However, these slightly different concentrations and depths may beexpressed as “substantially the same”.

[0041] In the well region 20, a p⁺-type impurity doped region 30 isformed for providing an ohmic contact. The impurity doped region 30 hasa relatively high impurity concentration and is formed by utilizing thesame process as that of forming the impurity doped regions 14 and 16.

[0042] The principal surface of the substrate 10 is covered with aninsulating film 32 including a field insulating film of silicon oxide orthe like. Wiring apertures are formed through the insulating film 32 asshown in FIG. 1. The impurity doped region 14 is connected to an inputterminal IN. The impurity doped regions 16 and 18 are connected to theimpurity doped region 26. The impurity doped regions 28 and 30 areconnected to a reference potential level (ground level).

[0043]FIG. 2 is an equivalent circuit diagram of the integratedstructure shown in FIG. 1. The emitter (impurity doped region 14) of thePNP transistor PB is connected to the input terminal IN. The collector(impurity doped region 16) of the transistor PB is connected to thecollector (well region 22) of the NPN transistor NB, and the base of thetransistor PB is connected to the collector of the transistor NB via aresistor R₁ made of the resistance component of the well region 12. Aconnection point between the base of the transistor PB and the resistorR₁ is represented by a node N₁. The anode and cathode of a diode D₁formed between the impurity doped region 14 and well region 12 areconnected to the emitter and base of the transistor PB, respectively.

[0044] The emitter (well region 24) of the transistor NB is connected tothe reference potential level, and the base of the transistor NB isconnected to the reference potential level via a resistor R₃ made of theresistance component of the well region 20. The cathode and anode of adiode D₃ made of a PN junction between the well region 22 and wellregion 20 and between the well region 22 and substrate 10 are connectedto the collector and base of the transistor NB, respectively. Aconnection point between the cathode of the diode D₃ and the collectorof the transistor NB is represented by a node N₂ and a connection pointbetween the base of the transistor NB and the resistor R₃ is representedby a node N₃.

[0045] The cathode of a diode D₂ made of a PN junction between the wellregion 12 and substrate 10 is connected to the cathode of the diode D₁,and the anode of the diode D₂ is connected to the anode of the diode D₃via a resistor R₂ made of the resistance component of the substrate 10,and to the ground level via a resistor R₄ made of the resistancecomponent of the substrate 10 and p-type well 20. A connection pointbetween the resistors R₂ and R₄ is represented by a node N₄.

[0046] The equivalent circuit of the transistor NB shown in FIG. 2 hasan emitter-base-collector layout shown in FIG. 3. A cross sectional viewtaken along line X-X′ shown in FIG. 3 corresponds to the cross sectionalview of the well region 20 shown in FIG. 1.

[0047] In the transistor NB shown in FIG. 3, the n-type well regions 22and 24 are formed inward spaced apart from two sides 20A and 20B of thep-type well region 20, and have the n⁺-type impurity doped regions 26and 28 inside the well regions 22 and 24. There are resistancecomponents R₃₁ and R₃₂ corresponding to the resistor R₃ shown in FIG. 2,between the p⁺-type impurity doped region 30 as a base contact regionand the p-type base region between the well regions 22 and 24.

[0048] The emitter-base-collector layout of the transistor NB may use alayout shown in FIG. 4. A cross sectional view taken along line Y-Y′shown in FIG. 4 corresponds to the cross sectional view of the wellregion 20 shown in FIG. 1.

[0049] In the transistor NB shown in FIG. 4, the n-type well regions 22and 24 are formed to extend outward from the two sides 20A and 20B ofthe p-type well region 20, to form a PN junction with the substrate. Then-type well regions 22 and 24 have therein the n⁺-type impurity dopedregions 26 and 28, respectively. Well regions 20 a and 20 b may beseparated from the well region 20 by the well regions 22 and 24 havingthe above-described pattern.

[0050]FIG. 5 is an equivalent circuit diagram of the transistor NBhaving the layout shown in FIG. 4. In FIG. 5, like elements to thoseshown in FIG. 2 are represented by like reference symbols. There is aresistor R₄₁ made of the resistance component of the substrate 10,between the base region BS of the p-type well region 20 b between then-type well regions 22 and 24 and the anode of the diode D₃. There is aresistor R₄₂ made of the resistance component of the substrate 10,between the base region BS and the p-type impurity doped region 30serving as the base contact region.

[0051] In the input protection circuit shown in FIGS. 1 and 2, when anESD input of, e.g., +2000 V is applied to the input terminal, the diodeD₁ turns on and a backward voltage is applied across the diode D₃ viathe node N₁, resistor R₁ and node N₂. When this backward voltage exceedsthe inverse breakdown voltage of the diode D₃, the base current of thetransistor NB increases. Therefore, the transistor NB turns on and alarge current flows. The voltage at the input terminal IN lowers at aninstant to +10 to +20 V to protect the subject circuit CP to beprotected.

[0052] If the circuit shown in FIG. 5 is used, the backward current ofthe diode D₃ flows through the node N₄, and resistors R₄₁ and R₄₂, andthe base current of the transistor NB increases. Therefore, thetransistor NB turns on and a large current flows. The protectionoperation similar to the circuit shown in FIG. 2 can therefore beperformed.

[0053] When an ESD input of, e.g., −2000 V is applied to the inputterminal IN, a forward voltage is applied across the diode D₃ via theresistor R₃ and node N₃ so that the diode D₃ turns on. A backwardvoltage is applied across the diode D₁ via the node N₂, resistor R₁ andnode N₁. In this case, the emitter and collector of the transistor NBshown in FIG. 2 become the collector and emitter, respectively. When thevoltage across the diode D₁ exceeds the inverse breakdown voltage of thediode D₁, the backward current of the diode D₁ flows through theresistor R₁ and node N₁ and the base current of the transistor PBincreases. Therefore, the transistor PB turns on and a large currentflows. The voltage at the input terminal IN rises at an instant to −10to −20 V to protect the subject circuit CP to be protected.

[0054] If the circuit shown in FIG. 5 is used, the protection operationsimilar to the circuit shown in FIG. 2 can be performed, excepting thata forward voltage is applied across the diode D₃ via the resistors R₄₂and R₄₁ and node N₄.

[0055]FIG. 6 shows an example of the voltage-current characteristics ofthe input protection circuit shown in FIGS. 1 and 2. A voltage appliedto the input terminal IN is represented by ±Vin (V), and a currentflowing through the input terminal IN upon application of the voltage±Vin is represented by ±lin (A). A curve +S shows the voltage-currentcharacteristics at +Vin, and a curve −S shows the voltage-currentcharacteristics at −Vin.

[0056] As shown in FIG. 6, the breakdown voltage at +Vin is about 18.5V, and the breakdown voltage at −Vin is about 15 V. The breakdownvoltage at +Vin corresponds approximately to the inverse breakdownvoltage of the diode D₃, whereas the breakdown voltage at −Vincorresponds approximately to the inverse breakdown voltage of the diodeD₁. The inverse breakdown voltage of the diode D₃ can be set as desiredby the impurity dope amounts of the well regions 20 and 22 and substrate10. For example, it can be set to about 18 to 50 V. The inversebreakdown voltage of the diode D₁ can be set as desired by the impuritydope amounts of the impurity doped region 14 and well region 12. Forexample, it can be set to about 13 to 15 V. Some audio IC is required toinput a signal in the signal level range of −12.5 V to +17.5 V. Suchrequirements can be met sufficiently by the input protection circuithaving the voltage-current characteristics shown in FIG. 6. According tothe characteristics shown in FIG. 6, the leak current in the range from−12.5 V to +17.5 V has a low level smaller than 1 μA.

[0057] In the input protection circuit shown in FIGS. 1 and 2, a currentlimiting resistor Ri made of resistive material such as polysilicon maybe formed on the insulating film 32 as shown in FIG. 1, and the inputterminal IN is connected to the p⁺-type impurity doped region 14(emitter of the transistor PB) via the resistor Ri as indicated bybroken lines in FIG. 1. The resistor Ri limits current so that it ispossible to prevent thermal breakage of circuit elements such astransistors PB and NB and diodes D₁ to D₃.

[0058]FIG. 7 is an equivalent circuit diagram showing a firstmodification of the integrated structure shown in FIG. 1 having invertedconductivity types.

[0059] This modification shown in FIG. 7 has elements havingconductivity types inverted from those of the integrated structure shownin FIG. 1. Namely, the conductivity type of the substrate 10 is changedto an n-type, the conductivity type of the well regions 12, 22 and 24 ischanged to a p-type, the conductivity type of the well region 20 ischanged to an n-type, the conductivity type of the impurity dopedregions 14, 16 and 30 is changed to an n⁺-type, and the conductivitytype of the impurity doped regions 18, 26 and 28 is changed to ap⁺-type. Therefore, the transistors PB and NB shown in FIG. 2 arechanged to an NPN transistor NB₁ and a PNP transistor PB₁, the diodesD₁, D₂ and D₃ shown in FIG. 2 are changed to diodes D₁₁, D₁₂ and D₁₃with inverted polarities. Resistors R₁₁, R₁₂, R₁₃ and R₁₄ and nodes N₁₁,N₁₂ and N₁₃ shown in FIG. 7 correspond to the resistors R₁, R₂, R₃ andR₄ and nodes N₁, N₂ and N₃ shown in FIG. 2.

[0060] In the circuit shown in FIG. 7, when an ESD input of, e.g., +2000V is applied to the input terminal IN, a backward voltage is appliedacross the diode D₁₁. When this backward voltage exceeds the inversebreakdown voltage of the diode D₁₁, the backward current of the diodeD₁₁ flows through the node N₁₁ and resistor R₁₁ and the base current ofthe transistor NB₁ increases. Therefore, the transistor NB₁ turns on.When an ESD input of, e.g., −2000 V is applied to the input terminal IN,the diode D₁₁ turns on and a backward voltage is applied across thediode D₁₃. In this case, the emitter and collector of the transistor PB₁shown in FIG. 7 become the collector and emitter, respectively. When thevoltage across the diode D₁₃ exceeds the inverse breakdown voltage ofthe diode D₁₃, the backward current of the diode D₁₃ flows through theresistor R₁₃ and node N₁₃ and the base current of the transistor PB₁increases. Therefore, the transistor PB₁ turns on. The subject circuitCP to be protected can therefore be protected from the ESD input of±2000 V.

[0061] In the circuit shown in FIG. 7, the positive signal level capableof being input is limited by the inverse breakdown voltage of the diodeD₁₁, whereas the negative signal level capable of being input is limitedby the inverse breakdown voltage of the diode D₁₃. The inverse breakdownvoltage of the diode D₁₃ is usually higher than the inverse breakdownvoltage of the diode D₁₁ so that a signal in the range, for example,from −50 V to +15 V can be input.

[0062] In the circuit shown in FIG. 7, the structures shown in FIGS. 4and 5 may be applied to the transistor PB₁. Similar to that describedwith reference to FIGS. 1 and 2, a resistor Ri may be connected betweenthe input terminal IN and the collector of the transistor NB₁ to limitthe current and prevent thermal breakage of the circuit components suchas transistors and diodes.

[0063]FIG. 8 shows a second modification of the integrated structureshown in FIG. 1. In FIG. 8, like elements to those shown in FIG. 1 arerepresented by like reference symbols.

[0064] In this modification shown in FIG. 8, the positions of the PNPtransistor PB and NPN transistor NB are replaced. Namely, in oneprincipal surface area of a p-type substrate 10, a p-type well region 40is formed having a relatively low impurity concentration. In the wellregion 40, n-type well regions 42 and 44 are formed which form an NPNlateral bipolar transistor NB₂ with a portion of the well region 40serving as its base. The well regions 42 and 44 have a relatively lowimpurity concentration and both provide a PN junction with the wellregion 40 and substrate 10 (or only with the well region 40). In thewell regions 42 and 44, n⁺-type impurity doped regions 46 and 48 areformed having a relatively high impurity concentration to provide ohmiccontacts. A p⁺-type impurity doped region 50 is formed in the wellregion 40 to provide an ohmic contact.

[0065] In the principal surface area of the substrate 10, an n-type wellregion 52 having a relatively low impurity concentration is formedhaving a PN junction with the substrate 10. In the well region 52,p⁺-type impurity doped regions 54 and 56 are formed to form a PNPlateral bipolar transistor PB₂ with a portion of the well region 52serving as its base. The impurity doped regions 54 and 56 have arelatively high impurity concentration. In the well region 52, ann⁺-type impurity doped region 58 is formed to provide an ohmic contact.

[0066] The impurity doped region 46 is connected to the input terminalIN. The impurity doped regions 48 and 50 are connected to the impuritydoped region 54. The impurity doped regions 56 and 58 are connected tothe reference potential.

[0067]FIG. 9 is an equivalent circuit diagram of the integratedstructure shown in FIG. 8. The collector (well region 42) of the NPNtransistor NB₂ is connected to the input terminal IN. The emitter (wellregion 44) of the transistor NB₂ is connected to the emitter (impuritydoped region 54) of the PNP transistor NB₂, and the base of thetransistor NB₂ is connected to the emitter of the transistor PB₂ via aresistor R₂₁ made of the resistance component of the well region 40. Aconnection point between the base of the transistor NB₂ and the resistorR₂₁ is represented by a node N₂₁. The cathode and anode of a diode D₂₁made of a PN junction between the well region 42 and well region 40 andbetween the well region 42 and substrate 10 are connected to thecollector and base of the transistor NB₂, respectively.

[0068] The collector (impurity doped region 56) of the transistor PB₂ isconnected to the reference potential, and the base of the transistor PB₂is connected to the reference potential via a resistor R₂₃ made of theresistance component of the well region 52. The anode and cathode of adiode D₂₂ made of a PN junction between the impurity doped region 54 andwell region 52 are connected to the emitter and base of the transistorPB₂, respectively. A connection point between the anode of the diode D₂₂and the emitter of the transistor PB₂ is represented by a node N₂₂, anda connection point between the base of the transistor PB₂ and theresistor R₂₃ is represented by a node N₂₃.

[0069] A resistor R₂₂ made of the resistance component of the substrate10 is connected between the anode of the diode D₂₁ and the node N₂₂. Thecathode of a diode D₂₃ made of a PN junction between the well region 52and substrate 10 is connected to the node N₂₃, and the anode of thediode D₂₃ is connected to the node N₂₂ via a resistor R₂₄ made of theresistance component of the substrate 10.

[0070] In the input protection circuit shown in FIGS. 8 and 9, when anESD input of, e.g., +2000 V is applied to the input terminal IN, abackward voltage is applied across the diode D₂₁. When this backwardvoltage exceeds the inverse breakdown voltage of the diode D₂₁, thebackward current of the diode D₂₁ flows through the node N₂₁ andresistor R₂₁ and the base current of the transistor NB₂ increases.Therefore, the transistor NB₂ turns on. When an ESD input of, e.g.,−2000 V is applied to the input terminal IN, the diode D₂₁ turns on anda backward voltage is applied across the diode D₂₂. In this case, theemitter and collector of the transistor PB₂ shown in FIG. 9 become thecollector and emitter, respectively. When the voltage across the diodeD₂₂ exceeds the inverse breakdown voltage of the diode D₂₂, the backwardcurrent of the diode D₂₂ flows through the resistor R₂₃ and node N₂₃ andthe base current of the transistor PB₂ increases. Therefore, thetransistor PB₂ turns on. The subject circuit CP to be protected cantherefore be protected from the ESD input of ±2000 V.

[0071] In the input protection circuit shown in FIGS. 8 and 9, thepositive signal level capable of being input is limited by the inversebreakdown voltage of the diode D₂₁, whereas the negative signal levelcapable of being input is limited by the inverse breakdown voltage ofthe diode D₂₂. The inverse breakdown voltage of the diode D₂₁ is usuallyhigher than the inverse breakdown voltage of the diode D₂₂ so that asignal in the range, for example, from −15 V to +50 V can be input.

[0072] In the input protection circuit shown in FIGS. 8 and 9, thestructures shown in FIGS. 4 and 5 may be applied to the transistor NB₂.Similar to that described with reference to FIG. 7, the conductivitytype inverted from that shown in FIG. 8 may be used. In this case, inthe equivalent circuit shown in FIG. 9, the transistors NB₂ and PB₂ arechanged to a PNP transistor and an NPN transistor, respectively, and thepolarities of the diodes D₂₁ to D₂₃ are inverted. In the protectionoperation, for an ESD input of +V, the NPN transistor turns on, and foran ESD input of −V, the PNP transistor turns on. The signal levelcapable of being input can be set, for example, in the range from −50 Vto +15 V. In the circuit shown in FIGS. 8 and 9, similar to thatdescribed with reference to FIGS. 1 and 2, a resistor Ri may beconnected between the input terminal IN and the collector of thetransistor NB₂ to limit the current and prevent thermal breakage oftransistors and diodes.

[0073] The present invention has been described in connection with thepreferred embodiments. The invention is not limited only to the aboveembodiments. For example, the impurity doped regions 14, 16, 54 and 56and other impurity doped regions may be formed as deep well regionshaving a relatively low impurity concentration. In this case, theinverse breakdown voltage of the diodes such as the diodes D₁ and D₂₂can be raised further and the range of the signal level capable of beinginput can be broadened further. In the structure shown in FIG. 4, thewell regions 20, 20 a and 20 b may be omitted and the base region BS ofthe transistor NB may be made of a portion of the substrate 10. In thiscase, the inverse breakdown voltage of the diodes such as the diodes D₃and D₂₂ can be raised further and the range of the signal level capableof being input can be broadened further.

What we claim are:
 1. An input protection circuit comprising: an inputterminal for supplying an input signal to a circuit to be protected; asemiconductor substrate of a first conductivity type; a first wellregion of a second conductivity type opposite to the first conductivitytype, said first well region being formed in one principal surface areaof said semiconductor substrate and forming a PN junction with saidsemiconductor substrate; first and second impurity doped regions of thefirst conductivity type formed in said first well region and forming afirst lateral bipolar transistor with a portion of said first wellregion serving as a base; a second well region of the first conductivitytype formed in the principal surface area of said semiconductorsubstrate; and third and fourth well regions of the second conductivitytype formed in said second well region and forming a second lateralbipolar transistor with a portion of said second well region serving asa base, bottoms of said third and fourth well regions forming a PNjunction with said second well or with said semiconductor substrate,wherein said input terminal is connected to said first impurity dopedregion, said second impurity doped region and the base of said firstlateral bipolar transistor are connected to said third well region, andsaid fourth well region and the base of the second lateral bipolartransistor are connected to a reference potential.
 2. An inputprotection circuit according to claim 1, further comprising a currentlimiting resistor formed on an insulating layer formed in the principalsurface area of said semiconductor substrate, wherein said inputterminal is connected via said current limiting resistor to said firstimpurity doped region.
 3. An input protection circuit comprising: aninput terminal for supplying an input signal to a circuit to beprotected; a semiconductor substrate of a first conductivity type; afirst well region of the first conductivity type formed in one principalsurface area of said semiconductor substrate; second and third wellregions of a second conductivity type opposite to the first conductivitytype, said second and third well regions being formed in said first wellregion and forming a first lateral bipolar transistor with a portion ofsaid first well region serving as a base, bottoms of said second andthird well regions forming a PN junction with said first well or withsaid semiconductor substrate; a fourth well region of the secondconductivity type formed in the principal surface area of saidsemiconductor substrate and forming a PN junction with saidsemiconductor substrate; and first and second impurity doped regions ofthe first conductivity type formed in said fourth well region andforming a second lateral bipolar transistor with a portion of saidfourth well region serving as a base, wherein said input terminal isconnected to said second well region, said third well region and thebase of said first lateral bipolar transistor are connected to saidfirst impurity doped region, and said second impurity doped region andthe base of the second lateral bipolar transistor are connected to areference potential.
 4. An input protection circuit according to claim3, further comprising a current limiting resistor formed on aninsulating layer formed in the principal surface area of saidsemiconductor substrate, wherein said input terminal is connected viasaid current limiting resistor to said second well region.
 5. An inputprotection circuit comprising: an input terminal for supplying an inputsignal to a circuit to be protected; a semiconductor substrate of afirst conductivity type; a first well region of a second conductivitytype opposite to the first conductivity type, said first well regionbeing formed in one principal surface area of said semiconductorsubstrate and forming a PN junction with said semiconductor substrate;first and second impurity doped regions of the first conductivity typeformed in said first well region and forming a first lateral bipolartransistor with a portion of said first well region serving as a base;and second and third well regions of the second conductivity type formedin the principal surface area of said semiconductor substrate, saidsecond and third well regions forming a second lateral bipolartransistor with a portion of said semiconductor substrate serving as abase, wherein said input terminal is connected to said first impuritydoped region, said second impurity doped region and the base of saidfirst lateral bipolar transistor are connected to said second wellregion, and said third well region and the base of the second lateralbipolar transistor are connected to a reference potential.
 6. An inputprotection circuit according to claim 5, further comprising a currentlimiting resistor formed on an insulating layer formed in the principalsurface area of said semiconductor substrate, wherein said inputterminal is connected via said current limiting resistor to said firstimpurity doped region.
 7. An input protection circuit comprising: aninput terminal for supplying an input signal to a circuit to beprotected; a semiconductor substrate of a first conductivity type; firstand second well regions of a second conductivity type opposite to thefirst conductivity type, said first and second well regions beingforming on one principal surface area of said semiconductor substrateand forming a first lateral bipolar transistor with a portion of saidsemiconductor substrate serving as a base; a third well of the secondconductivity type formed in the principal surface area of saidsemiconductor substrate and forming a PN junction with saidsemiconductor substrate; and first and second impurity doped regions ofthe first conductivity type formed in said third well region and forminga second lateral bipolar transistor with a portion of said third wellregion serving as a base, wherein said input terminal is connected tosaid first well, said second well region and the base of said firstlateral bipolar transistor are connected to said first impurity dopedregion, and said second impurity doped region and the base of the secondlateral bipolar transistor are connected to a reference potential.
 8. Aninput protection circuit according to claim 7, further comprising acurrent limiting resistor formed on an insulating layer formed in theprincipal surface area of said semiconductor substrate, wherein saidinput terminal is connected via said current limiting resistor to saidfirst well region.
 9. A semiconductor input protection circuitcomprising: a semiconductor substrate; a first active region of a firstconductivity type defined in said semiconductor substrate; a secondactive region of a second conductivity type defined in saidsemiconductor substrate; first and second impurity doped regions of thesecond conductivity type formed in said first active region; third andfourth impurity doped regions of the first conductivity type formed insaid second active region; an input terminal connected to said firstimpurity doped region; a first wiring for connecting said first activeregion and said second impurity doped region to said third impuritydoped region; and a second wiring for connecting said second activeregion and said fourth impurity doped region to a reference potential.10. A semiconductor input protection circuit according to claim 9,wherein said semiconductor substrate is of the second conductivity typeand said third and fourth impurity doped regions reach a bottom of saidsecond active region.
 11. A semiconductor input protection circuitaccording to claim 9, wherein said semiconductor substrate is of thefirst conductivity type and said first and second impurity doped regionsreach a bottom of said first active region.
 12. A semiconductor inputprotection circuit according to claim 10, wherein said second activeregion is a portion of said semiconductor substrate.
 13. A semiconductorinput protection circuit according to claim 11, wherein said firstactive region is a portion of said semiconductor substrate.
 14. Asemiconductor input protection circuit according to claim 9, furthercomprising: an insulating film formed on said semiconductor substrate;and a polysilicon resistor formed on said insulating film, wherein saidinput terminal is connected via said polysilicon resistor to said firstimpurity doped region.
 15. A semiconductor input protection circuitaccording to claim 9, further comprising: a first contact region of thefirst conductivity type having a high impurity concentration, and formedin said first active region outside said first and second impurity dopedregions, wherein said first wiring is connected via said first contactregion to said first active region.
 16. A semiconductor input protectioncircuit according to claim 15, wherein said first contact region andsaid third and fourth impurity doped regions have substantially the sameimpurity concentration and depth.
 17. A semiconductor input protectioncircuit according to claim 9, further comprising: a second contactregion of the second conductivity type having a high impurityconcentration, and formed in said second active region outside saidthird and fourth impurity doped regions, wherein said second wiring isconnected via said second contact region to said second active region.18. A semiconductor input protection circuit according to claim 15,wherein said second contact region and said first and second impuritydoped regions have substantially the same impurity concentration anddepth.
 19. A semiconductor input protection circuit according to claim10, further comprising: a first contact region of the first conductivitytype having a high impurity concentration, and formed in said firstactive region outside said first and second impurity doped regions,wherein said third and fourth impurity doped regions each include asurface side high impurity concentration region and a deeper lowimpurity concentration region, and have substantially the same impurityconcentration and depth as said surface side high impurity concentrationregion and said first contact region.
 20. A semiconductor inputprotection circuit according to claim 11, further comprising: a secondcontact region of the second conductivity type having a high impurityconcentration, and formed in said second active region outside saidthird and fourth impurity doped regions, wherein said first and secondimpurity doped regions each include a surface side high impurityconcentration region and a deeper low impurity concentration region, andhave substantially the same impurity concentration and depth as saidsurface side high impurity concentration region and said second contactregion.